Modelling of Guardband Reduction on Design Area

Considering fabrication variations, timing guardband is introduced to ensure design reliability. However, trade-off exists between guardband and design performance, especially the chip area discussed in this paper. To predict the variation of total chip area with guardband reduction, we construct the model from the basic Elmore delay theory and optimize the gate sizing and buffering to meet the setup timing constrains. To determine the coefficients in the model, we utilize the empirical results from the Synthesis, Placement and Routing implementation flow and employ nonlinear fitting method. Furthermore, the testing on our model exhibits high accuracy and capability of predicting.